1. Field of the Invention
This invention relates generally to the structure and fabrication process of trenched DMOS transistors. More particularly, this invention relates to a novel and improved DMOS structure and fabrication process wherein reduced number of masks are employed such that the DMOS devices can be manufactured at lower cost and additionally, the device ruggedness is strengthened and the source contact resistance is reduced.
2. Description of the Prior Art
The fabrication cost of a semiconductor device is often adversely affected due to an increase in the number of masks required in the fabrication process. The fabrication cost for a double-diffusion metal oxide semiconductor (DMOS) device is kept at a relative high level when applying the conventional fabrication methods. The more rigid cost structure for DMOS fabrication is due to the technical difficulty that the number of masks required in device fabrication cannot be easily reduced. Cost reduction in DMOS fabrication is therefore not achievable when the required number of masks remains unchanged.
In addition to the consideration of fabrication costs, the production yield is increased when the number of masks employed in the fabrication process is reduced. A simplified fabrication process with less masks generally reduces the uncertainties and uncontrollable factors during fabrication and leads to yield rate improvement. Again, in the conventional DMOS fabrication techniques, simplified fabrication process with reduction of mask requirements is not easily achievable and yield improvement is still a goal beyond reach.
The number of masks required in DMOS fabrication is closely related to the structure of a DMOS transistor. Please refer to FIGS. 1A and 1B for a general device structure of a planar DMOS transistor 10 and 10' respectively where a cross-sectional views of typical DMOS cells 10 and 10' in the core cell region are shown. The DMOS transistor is supported on a N+ substrate 15 and an N-epi-taxial layer 20 formed on its top. The cell 10 includes a deep p.sup.+ -body region 25, a shallow p body 26, a source region 30 wherein the source region 30 and the p-body region 26 surround a gate 40 insulated by a gate oxide layer 35. The DMOS cell 10 is then covered with a PSG or BPSG protection layer 45. A contact 50 is then formed on top of the source region 30. The DMOS structures as shown for both the planar and trenched DMOS require that the source regions 30 be shorted to the body 25 where a channel is formed for conducting a source-to-drain current. This general structural feature imposes the following basic requirements on the fabrication processes:
(1) The deep p.sup.+ regions 25 and the p-body regions 26 are usually formed prior to the formation of the source regions 30; and PA1 (2) Subsequent to the formation of the p-body region 26, the source regions 30 are then formed within the p-body regions 26 wherein the source regions 30 are shallower and have a different cross-sectional profile than the p-body regions 26.
Due to the facts that the source regions 30 are formed with different cross sectional profile than that of the p-body region 26, in a conventional DMOS fabrication process, two separate masks are usually applied to form the deep p.sup.+ regions 25 and the source regions. Several technical approaches are applied in the prior art as described below with some of these techniques employed to reduce the number of masks required in DMOS fabrication by eliminating the requirement for a separate mask for source implant. However, as will be further explained below, these prior art techniques for DMOS fabrication, even with reduced number of masks, are still limited by other technical difficulties.
FIG. 2 depicts a typical prior art approach used to form the source regions 30 in a p-body region 26. A source mask is applied to form a plurality of photoresist blocks 55 above the source regions 30. A source implant with ion beam 60 is then carried out. Part of the ion beam is blocked by the photoresist blocks 55 in forming the source regions 30. Due to the fact that in this traditional fabrication process, a separate source mask is required to form the source block 55, many invention disclosed in several US Patents provide new approaches to eliminate the use of this separate source mask.
In a U.S. Pat. No. 4,443,931, entitled "Method of Fabricating a Semiconductor Device with a Base Region Having a Deep Portion" (issued on Apr. 24, 1984), Baliga et al. disclose a MOSFET device. The MOSFET device is fabricated by depositing a LPCVD nitride layer after the poly gate is etched. A p.sup.+ mask is applied to open a p.sup.+ -diffusion window. A p-type dopant is then diffused through the p.sup.+ diffusion window. A thick oxide layer is then thermally grown over the p.sup.+ diffusion window. An active mask is applied to selective etch the initial oxide layer. Because the oxide layer grown over the p.sup.+ diffusion window has a greater thickness, an oxide plug is left covering a portion of the p.sup.+ -diffusion window after the etching process. The oxide plug is then applied as a block for source implant. This method is limited by the difficulty that the transistor cannot be shrunk due to a consideration that the deep p.sup.+ region may encroach the channel when the core cells are fabricated with reduced dimension. The fabrication technique is also practically limited in its usefulness due to the more complicate processes.
In another patent, Baliga et al. in U.S. Pat. No. 4,567,641 entitled "Method of Fabricating Semiconductor Devices Having A Diffused Region of Reduced Length" disclose a method of fabricating a semiconductor device where the requirement of a source blocking mask is eliminated. The processing steps are shown in FIGS. 3A to 3D. (FIGS. 4A to 4D in Baliga's Patent). In FIG. 3A, a semiconductor body 200, e.g., a silicon wafer, includes a substrate 202 constituting an N.sup.+ -drain and a N-region 204. On the upper surface 205 of the body 200, an insulating layer 206 is formed followed by deposition of a layer 208 composed of a doped polysilicon material on the insulating layer 206. Another insulating layer of silicon oxide is grown on top of the polysilicon layer 208. Finally, a layer 211 composed of aluminum oxide is deposited on top of the oxide layer 210. A photolithography process is then employed to produce a mask 216 as that shown in FIG. 3B which defines a window 217 and serves as a diffusion barrier when a P-type diffusion through the window 217 is made to form the P base 218.
In FIG. 3C, A N+ diffusion is made through the window 217 to form a N+ source region 220 which extends laterally beneath the polysilicon layer 208 thus forming a region 222 with the lateral diffusion distance approximately the same distance diffused in the downward-vertical direction. The diffusion of the N+ region occurs at an elevated temperature in an oxidizing atmosphere. As a result, the exposed surface 219 (shown in FIG. 3B) becomes oxidized and forming an oxide layer 221. In FIG. 3D, an anisotropic etchant to the oxide layer 221 through the window 217 is applied. This etchant etches through the oxide layer 221 substantially all the way through the N+ region 220 while allows the shoulder 223 of the N+ source 220 to remain intact. Specifically, the anisotropic etchant can be a vertically collimated-beam of reactive ions or a planar plasma etchant and forms a generally U-shaped groove 224. Alternatively, a V-shaped groove could be formed. Thus the source regions 220 are formed in the P base region 218 without requiring the use of a source mask.
The semiconductor device disclosed by Baliga et al., in U.S. Pat. No. 4,567,641, is limited by the fact that the DMOS fabrication process as disclosed involves a more complicate procedure where anisotropic etch is to be performed to etch a silicon groove through the oxide layer. Such procedure is more difficult to perform and therefore more costly. The device by Baliga et al. has another technical limitation that the contact-resistance resistance is relative high due to a reduction of n.sup.+ contact area because only the N+ side-walls are in contact with metal when the U-shape groove is formed in the P region 218. For those reasons, even that the fabrication procedure disclosed by Baliga et al. is able to eliminated the mask used for source implant, does not provide an effective device fabrication method due to its higher contact-resistance and more complicated fabrication procedures.
Another difficulty faced by those engaged in power MOSFET manufacture in attempt to reduce the production cost by reducing the number of required number of masks is the concerns related to device ruggedness. A designer is faced with a constant challenge to increase the device ruggedness due to the fact that various internal parasitic components often impose design and performance limitations to a conventional power metal oxide silicon field effect transistor (MOSFET). Among these parasitic components in a MOSFET transistor, special care must be taken in dealing with a parasitic npn bipolar junction transistor (BJT) formed between the source, the body, and the drain. Under normal static conditions the base and emitter of the parasitic BJT are shorted, leaving only the body-drain diode effective. However, in a transient conditions and during an avalanche breakdown, the parasitic BJT may be activated incidentally which can seriously degrade the overall performance of the MOSFET. Under the circumstances when the parasitic bipolar junction transistor is incidentally activated, snap back may occur which can cause permanent damages to the device. For this reason, precaution must be taken to increase the ruggedness of the device by taking into account that an incidental activation of the parasitic BJT should be prevented in an avalanche breakdown condition when large amount of hole current is generated in the core cell area.
For the purpose of improving device ruggedness, more complicate manufacture processes are often applied which involve either the use of implant mask to form a buried body implant region under the source region or the formation of spacer. Either of these approaches leads to increase in production costs due to the more elaborate and complicate manufacture processes. Device reliability is often adversely affected due to the degradation of gate oxide when spacers are employed to form the self-aligned buried body regions. Because of these difficulties, those of ordinary skill in the art are still limited by the dilemma that the goal of cost reduction by simplifying manufacture processes with reduced number of masks appears to run against another design goal of improving the device ruggedness. Several prior art Patents disclose methods to increase device ruggedness, e.g., U.S. Pat. No. 5,119,153 by Korman et al., and U.S. Pat. No. 5,268,586 by Mukherjee et al., are clear illustrations of the technical difficulties faced by those engaged in DMOS design and manufacture today.
Therefore, there is still a need in the art of power device fabrication, particularly for DMOS design and fabrication, to provide a structure and fabrication process that would resolve these difficulties.